Events
Low-Power Verification - bridging the gap between hardware and software
- Venue:
Rutherford Appleton Laboratory, Oxfordshire, OX11 0QX
- Date:
- Tue 21 Jun 2011
- Time:
- 900 - 1600
- Cost:
No charge to attend for NMI members and invited guests
- Booking Details:
This event is nearly full, so we are managing registrations via a waiting list. Register for a place here
Predicting the power consumption of hardware is always a challenge. However any semblance of accuracy is completely dwarfed by the use cases which are now almost entirely driven by software. Engineers face the dilemma of either over-designing for the worst-case or designing for 'typical' usage - with the risk that brings.
Agenda (download pdf version)
Note : presentations and the attendee list from this event are available in the members' area
09:00 Registration, refreshments and tabletop exhibitions
09:30 NMI, Robin Kennedy
Welcome and Introduction
ST Microelectronics, Paul Bailey
The SoC Power Estimation Challenge
University of Bristol, Kerstin Eder
Energy Aware Software - an overview of the state of the art
Break
Mentor Graphics, Alex Grove
Optimizing a Platform’s Application Power and Performance
University of Bristol/XMOS, Steve Kerrison
The XCore chip - understanding the impact of multi-threaded software on power consumption
Lauterbach, Barry Lock
Power by Software Function - some real life examples
13:00 Lunch
Doulos, John Aynsley
Software-driven Verification using SystemC TLM-2.0 Virtual Platforms
Cadence, Nick Heaton
Case Study : Hardware/Software Verification of low-power SoC using ISX
Panel Discussion - chaired by Mike Bartley, TVS
"Low Power : Taking a System Perspective"
1600 Close
One additional tabletop exhibition is available - please contact Robin Kennedy for more details.
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