International Conference on CMOS Variability "The Impact of Variability on Design"
Royal College of Physicians, London
- Tue 23 Oct 2007
Fact: There are fundamental changes in sight that will have a far-reaching impact for design and manufacturing in the semiconductor industry. At nodes at or below 45nm significant changes take place. At the device level variability means that there will be significant parametric differences from device to device on the same wafer.
Theme: The industry must learn "how to cope" with variability issues across three major areas: chip design, design automation tools and manufacturing technology How prepared is your organisation to understand the implications of these changes and manage the impact?
NMI in collaboration with the UK e-Science Pilot Project - "Meeting the Design Challenges of NanoCMOS Electronics" is providing a unique opportunity for system, chip and device designers, technology developers, EDA suppliers and wafer foundries to gain crucial insight from recoginised world experts from:
- IBM Watson Centre
- STARC Japan
- Mentor Graphics
- University of Glasgow
- (E-Science Project)
- University of Manchester
Networking with your peers cannot be understated - can you afford to miss it?
8:30 Registration and Refreshments
9:00 Welcome & Key Note
Welcome by the Rt. Hon. Stephen Timms MP, Minister for Competitiveness
"Welcome to the CMOS Variability Conference"
Key Note by Asen Asenov, University of Glasgow
"Variability in the next generation CMOS technologies and impact on design"
9:40 SESSION 1: Design Concepts
Bart Dierickx, IMEC: "Technology aware design"
Steve Furber, University of Manchester: "Dealing with variability in modern circuit design"
Masami Murakata, STARC: "DFM&Y- Research and development topics in STARC"
*** Coffee ***
11:30 SESSION 2: Design Implementation & Tools
Christophe Guittard, Mentor Graphics: "The serious impact of "variability" on traditional Place & Route"
Victor Moroz, Synopsys: "OPC corrections and strain - the impact on design"
Pierrick Pedron, Cadence: "SOC Encounter Statistical Design"
*** Buffet Lunch & Networking ***
14:00 SESSION 3: Semiconductor Technologies
David Frank, IBM: "High Performance CMOS variability in the 65nm regime and beyond"
Marcel Pelgrom, NXP: "Nanometer CMOS is a statistical challenge!"
Walter Ganzevles, TSMC: "Solutions for managing increased variability"
*** Coffee ***
15:50 SESSION 4: IP Development & Research
Yves Laplanche, ARM: "IP design: how sigma is changing our lives?""
16:15 PANEL: "Integration and Collaboration in the Era of Design for Variability (DfV)"
Chair: Asen Asenov
17:00 Conference Close immediately followed by:
Post-Conference Drinks Reception & Further Networking