Today, many forces at play contribute to the gap between what we can fabricate (silicon capacity) and what we have time to design. In addition, there are forces at play that contribute to a gap between what we can design and what we realistically have time to verify (within a project's schedule). Nonetheless, we tape out complex systems all the time. Hence, the question arises, is the productivity gap real? And if so, what can we do to minimize its effects? This talk provides a statistical analysis of today's industry trends in the adoption of advanced functional verification (AFV) techniques, and then offers new models for improving AFV maturity within an organization.

Biography:
Harry Foster is Chief Verification Scientist for Mentor Graphics. Prior to EDA, Harry has researched and developed functional verification tools and methodologies for over 12 years as a senior member of the CAD technical staff at Hewlett-Packard, and was an ASIC and board design engineer for 5 years at TI. Harry currently serves as chair of the Accellera Formal Verification Technical Committee, and chair of the IEEE 1850 Property Specification Language (PSL) working group. He is co-author of five books on verification. Harry holds multiple patents in functional verification. He is the original creator of the Accellera Open Verification Library (OVL) assertion monitor standard, and was the
2006 recipient of the Accellera Technical Excellence Award for his contributions to industry standards.

See http://www.cs.bris.ac.uk/Research/Micro for more details