OVERVIEW

Serma Technologies and Yole Développement propose to debate through a dedicated event jointly organized in Paris on November 8 to 10, 2011 with invited presentations by worldwide industrial players of both large global companies and SMEs.

2011 Program:
A conference with three sessions:

• Design - Industrialization - Packaging
• A debate at the end of each session
• A networking time all along the 3 days

 
Technology and supply chain challenges for fabless semiconductor companies

Fabless semiconductor companies constantly face the challenge of designing competitive products which can easily be manufactured by their manufacturing partners with good yields. Comprehensive access for their design, test and quality engineers to the design rules and guidelines is key to implement the required Design for Manufacturability (DfM) practices.

This becomes even more critical with the ever widening array of IC packaging technologies and solutions: how to make the right package platform choice for a given product? What is the most optimized trade-off between electrical and thermal performance, power consumption, reliability, size, manufacturability and cost of the packaged integrated circuit? How to find the right manufacturing partners for the chosen technology to minimize risks and costs? Should the technology choices influence the choice of the manufacturing partners, or should it be the other way round? How to access the latest 3D and Wafer Level Packaging technologies with controlled risks and without cost penalties? How can fabless companies also influence the evolution and road mapping of the semiconductor packaging and test industry?

These are the hot questions Serma Technologies and Yole Développement propose to debate through a dedicated event jointly organized in Paris on November 8 to 10, 2011 with invited presentations by worldwide industrial players of both large global companies and SMEs.

AGENDA

The agenda is preliminary, and subject to change. Check back often for the latest updates, or request to be notified of event updates by contacting Sandrine Leroy, Yole Développement.

Confirmed speakers : Dialog, LFoundry, STAT ChipPac, Unisem, XFab, Serma Technologies, Yole Développement...

November 8th, 2011

7.30 PM - Welcome Cocktail

November 9th, 2011

9.00 AM - Session 1: Industrialization

How to make semiconductor industrialization supply chain easier for fabless companies?
Today all the Semiconductor fabless companies have the same issues to ensure Time to Market or Time to volume. There are more and more suppliers to manage with different background: Wafer Fab, Test House, Packaging, FA Lab. This situation could be problematic when you need to optimize cost & time in order to be competitive on your market and answer your customer needs. Knowing that the product life is shorter, the good management of this situation became a success key factor. Major players will share their experience during this session.

1.00 PM – Networking lunch

2.00 PM - Session 2: Design

First time right designs are not only increasingly key to optimize time to market and development costs, but they also set to integrate an increasing number of parameters upfront way beyond the classical IC design of the sole “silicon crystals”. Packaging and testability require particular attention during the design phase so as to best use available or new technologies for low cost manufacturing. It is therefore a key challenge for fabless semiconductor companies to integrate these technologies and their suppliers into their design flows.

7.30 PM - Business Reception

November 10th, 2011

9.00 AM - Session 3 – Packaging

Never have semiconductor packaging technologies changed so radically and fast as they have been doing in the past years. Packaging accounts for a rising share of the mean IC build of material and IC packaging follows a fast moving trend to wafer level packaging and 3D integration. It is key for fabless semiconductor companies to understand and take part in this evolution so as to draw benefits for their products and influence this trend. When can the expected cost and performance levels be met with design optimizations and when is the use of new package platforms needed? How to make the right package and supplier choice? Examples and “field rules” will be given by semiconductor fabless.

1.00 PM – Networking Lunch

2.00 PM – End of SSF 2011