Event Host & Sponsor

National Physical Laboratory (NPL)

Directions

For Map and Directions to the NPL venue follow this LINK

Event Overview

" Cutting Corners Costs Quality "

Hosted this year by the National Physical Laboratory ( NPL ), the event will open with a highly stimulating key note address from Nihal Sinnadurai, CEO of ATTAC and a Distinguished Lecturer of IEEEon the theme - “Ticking Time-Bombs in Electronics and Photonics Systems and Networks”.

As Customer demands on Quality and Reliability become increasingly tough Companies must invest more by "designing in" ( DfR ) rather than trying to "screen out". The event will deal with a broad cross section of "Quality and Reliability Assurance" issues faced by UK Semiconductor companies. Experienced Industry speakers will cover views from both end user and technology ( chip ) supplier - complemented by a sample of case studies from analytical and reliability service suppliers.

In addition to our line up of exciting talks we invite you to join in our Panel debate around the topic of Quality Standards and their applications. Don't miss this opportunity to learn from our Industry experts about the benfits of investing in Quality/Reliability Assurance and why "Cutting Corners Costs Quality".

NPL Facility Tour

We would like to thank our host NPL for providing our delegates with an outstanding opportunity to join one of the four guided tours through the extensive NPL Laboratory facilities.

Agenda ( Download Agenda details) [193kB]

9:30am  Registration & Coffee

NMI, Paul Jarvie, Introduction and welcome

NPL, Kamal Hossain, Welcome to National Physical Laboratory.

Key Note Speaker :

Nihal Sinnadurai (CEO of ATTAC and a Distinguished Lecturer of IEEE) , Ticking Time-Bombs in Electronics and Photonics Systems and Networks

NPL, Alex Shard / Chris Hunt, Surface Analysis, PCB & Component Reliability            

Freescale Semiconductor, Ally Gorman, Designing in Automotive Quality  

Lauterback, Barry Lock  Taking the right decisions

12:40pm ~ 2:35pm  ** BUFFET LUNCH ,TABLE TOPS,  NPL LAB TOURS  **

Maser Engineering, Mark Gortemaker, Obsolete products application, a potential reliability hazard.

RCL / DfT Solutions, Stephen Meats/Eric Cormack, Applying the principles of DfX to correct design weaknesses found on first silicon  

Industry Forum, Arthur David   Managing Automotive standard TS16949

PANEL SESSION - "Do the Standards fit the application ? "

- Chaired by Nihal Sinnadurai (CEO of ATTAC and a Distinguished Lecturer of IEEE )

- Panel : NXP, NPL, Freescale Semiconductors, DfT Solutions

4:45 pm Event Close                     

 

Table Tops

The Table Top spaces are now fully occupied and we are delighted to have the following companies exhibiting at the event:

• RCL
• DfT Solutions
• Reltech
• Phasix
• Maser Engineering
• Dockweiler
• Parabilis
• Lauterbach
• JP Kummer