| Location: Thornbury Golf Centre, Bristol,
BS35 3XL |
| Please contact John
Moor if you have any queries regarding registration for this
event.
DDI: 07739 982327
Download the flyer
for this event.
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The need for improved productivity, efficiency and innovation are
imperatives for an industry that competes at the global level. System
Level Design is promoted as offering a route to deliver more efficient
designs, faster and more accurately through improved system level
definition, modelling, analysis and implementation methodologies.
The System Level Design (SLD) network has been established to explore
microelectronics system design from the system/algorithmic definition
level through to RTL/chip level. The network takes a hardware perspective
on system level design down to RTL level, linking with and complementing
other technical networks such as Embedded Software and Verification.
The System Level Design (SLD) network covers areas such as ;
- system definition
- making optimal hardware/software trade-offs
- system hardware implementation methodologies to RTL/chip level
- system level hardware verification methodologies.
- system integration
The SLD events provide a support forum and opportunity for the key
players active in SLD to network and exchange views.
Event Theme
Various analyses indicate that today’s large system on chip
designs re-use somewhere in the region of 80-90% legacy IP. This
event will explore SLD methodologies and the particular challenges
posed by designing for re-use and incorporating legacy IP.
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| 10.00 Registration and Refreshments
10.20
Welcome & Introduction,
Steve Cozens, Consultant
to NMI
10.30
Electronic System Level
(ESL): The New Approach to System Level Design
Dr David Greaves, Cambridge University
11.00 Comprehensive System
C Cycle Accurate TLM & OSCI update.
Automated ESL to improve implementation flow using SPIRIT
IP-XACT
Nizar Romdhane, ARM (also OSCI & SPIRIT)
11.30 ESL, a viable approach?
Jean-Marie Saint-Paul, Mentor Graphics
12.00 An Automotive perspective
on System Level Design and re-use of Legacy IP
Glenn Farrall, Infineon Technologies
12.30 Buffet Lunch & Networking
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13.30 Building
a Complete Electronic System Level (ESL) Design Flow
Dr Jeremy Bennett, Tenison
Design Automation
14.00 Virtual Platforms: from
concept to reality
Markus Willems, Synopsys
14.30 Panel Session
What are the opportunities
and challenges to building an efficient system level design
methodology incorporating legacy IP?
Chair: Chris Lennard, ARM
Panel:
Jeremy Bennett Tenison Design Automation
Robert Cottrell Altera
Andy Jones STMicroelectronics
Graham Kirsch Micron
Colin Tattersall Beach Solutions
15.30 End of Panel Session
& Networking
16.00 Close |
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