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9:30 Registration and Refreshments
10.00 Welcome & Introduction
Paul Jarvie, NMI
10.15 Key Note : "DfX challenges for SiP"
Alain Rougier, NXP Semiconductors
Eindhoven
10:45 65nm: Redefining the meaning of DRC sign-off
Ian Smith , Mentor Graphics
11:15 Manufacturing Aware IC Implentation Flow - Concurrent
yield and timing optimization
Claire Nauts, Cadence
11:45 The Foundry approach to DfM at sub 90nm
TBC
12.15 Buffet Lunch & Networking
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13.15 Meeting the Design Challenges of Nano-CMOS Electronics
Asen Asimov, University of Glasgow
13:45 DfM challenge for MEMS applications
Dave Guite, Innos
14:15 DfM and the SoC
Graham Curran, Sondrel (TBC)
14.45 Panel session –
Chair (John Moore – NXP Semiconductors)
“Where to invest the money and can the new face of DfM
provide more value?”
15.30 Further Networking / Close
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