Kelin J. Kuhn
Intel Fellow, Technology and Manufacturing Group

Kelin J. Kuhn is an Intel Fellow, Technology and Manufacturing Group and Director of Advanced Device Technology. Kuhn is responsible for device architecture path finding for Intel's advanced process technologies.

Kuhn joined Intel in 1997 working on Intel's 0.35 micron process technology. Since then, Kuhn has been involved in Intel's manufacturing process technology development for the 0.35 um, 130nm, 90nm, 45nm and 22nm technology nodes.

Previously, Kuhn was a tenured faculty member in the Department of Electrical and Computer Engineering at the University of Washington. Kuhn is the past recipient of a National Science Foundation Presidential Young Investigator Award for her work on strained layer III-V materials and an Intel IAA award for her work on Hi-K metal gate transistors. Kuhn has six patents with four others pending, is the author of more than 60 technical papers, and has authored a textbook on laser engineering.

Kuhn earned her bachelor's degree in electrical engineering from the University of Washington in 1980. Kuhn received her master's and doctoral degrees in electrical engineering from Stanford University in 1985.

Dr Sani Nassif
Manager, Tools and Technology Department, IBM

Sani received his PhD from Carnegie-Mellon university in the eighties. He worked for ten years at Bell Laboratories on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation.

He joined the IBM Austin Research Laboratory in January 1996 where he is presently managing the tools and technology department, which is focused on design/technology coupling and includes activities in: model to hardware matching, simulation and modeling, physical design, statistical modeling, statistical technology characterization and similar areas.

Jean-Marie Brunet
Mentor Graphics

Jean-Marie Brunet is the Director Product Marketing for Model Based DFM and Place-and-Route Integration at Mentor Graphics Corporation. Over the past 15 years, he has served in application engineering, marketing and management roles in the EDA industry, and has held IC design and design management positions at STMicrolectronics, Cadence, and Micron among others. His experience includes working with pure-play foundries to resolve complex yield issues related to OPC and RET. He holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France. Jean-Marie Brunet can be reached at jm_brunet@mentor.com

Krisztián Flautner
ARM

Krisztián Flautner is the vice president of research and development at ARM Ltd. ARM designs the technology that lies at the heart of advanced digital products with more than ten billion processors deployed by early 2008. He leads a global team which is focused on the understanding and development of technologies relevant to the proliferation of the ARM architecture. The groups activities cover a wide breadth of areas ranging from circuits, through processor and system architectures to tools and software. Key activities are related to high-performance computing in energy-constrained environments. Flautner received a PhD in computer science and engineering from the University of Michigan, where he is currently appointed as a visiting scholar. He is a member of the ACM and the IEEE.

Professor Asen Asenov
Department of Electronics and Electrical Engineering, University of Glasgow

Asen Asenov received his MSc degree in solid state physics from Sofia University, Bulgaria in 1979 and the PhD degree in physics from The Bulgarian Academy of Science in 1989. He is a professor of Device Modelling, Leader of the Glasgow Device Modelling Group and Academic Director of the Glasgow Process and Device Simulation Centre he coordinates the development of 2D and 3D quantum mechanical, Monte Carlo and classical device simulators and their application in the design of advanced and novel CMOS devices. He has pioneered the simulations of statistical variability in nano-CMOS devices including random dopants, interface roughness and line edge roughness. He has over 450 publications in the above areas.

Davide Pandini
Design Methodologies R&D manager, ST Microelectronics

Davide Pandini holds a Ph.D. degree in electrical and computer engineering from Carnegie Mellon University, Pittsburgh, PA. He was a research intern at Philips Research Labs. in Eindhoven, the Netherlands, and at Digital Equipment Corp., Western Research Labs. in Palo Alto, CA. He joined STMicroelectronics in Agrate Brianza, Italy, in 1995, where he is a Design Methodologies R&D manager and a senior member of the technical staff. His current research interests include signal integrity and interconnect modeling for DSM technologies, statistical analysis and optimization, asynchronous design, DFM and regular design, EMC/EMI. Dr. Pandini has authored and coauthored more than forty papers in international journals and conference proceedings, and during the academic years from 1998 to 2000, he was a visiting professor at the University of Brescia, Italy. He serves on the program committee of international conferences such as DAC, GLSVLSI, EMC-COMPO, PATMOS, ASYNC, and ESSDERC. Dr. Pandini received the ST Corporate STAR 2008 Gold Award for leading the R&D excellence team on EMC-aware design.

Nam Sung Kim
Chartered Semiconductors

Nam Sung Kim is currently a senior principal engineer in Technology Development Group of Chartered Semiconductor Manufacturing, Ltd. He is responsible for device design for advanced CMOS logic technologies including SRAM devices, currently(Aug., 2007-present) focusing on MG/HK technology in a joint development with the ISDA 32/28nm Bulk alliance partners in IBM East-Fishkill, New York.

He joined Hynix Semiconductor (previously, LG semiconductor) in 1995, working in development and manufacturing for various generation SDRAM technologies that included research and development as well as yield improvement by DRAM cell engineering. He returned to Systems on Silicon Manufacturing Co. Pte. Ltd. (SSMC, a joint venture of Philips (currently, NXP), TSMC and EDBI) in 2002 and worked as a section head in process integration for 0.13/0.15/0.18/0.25um CMOS Logic and Flash/EEPROM memory technologies. And, he moved to Chartered Semiconductor Manufacturing Ltd in 2006, and working in the field of device design development for 65/45nm low power and high performance technologies. His major and interesting field is a new device development and set up for advanced & leading edge CMOS logic technologies together with SRAM cell device development. He holds 17 registered patents, 2 pending patents domestic and worldwide about fabrication methods of deep sub-micron devices and he is also the author of more than 35 technical papers including journals. He earned his master's degree (Ms.c) for microelectronics in electrical and computer engineering at National University of Singapore.

Andrew Appleby
NXP Semiconductors

Andrew Appleby a Physical Design Technical Lead for NXP semicondutors. He was responsible for realising the Physical Design of NXP's first 45nm System on Chip. Andrew has 20 years of experience in Semiconductors R&D working primarily as an analogue designer, physical designer and project leader. He spent most of this time working for Philips semiconductors and laterly NXP semiconductors in Southampton UK, but also spent some time woking at STM Cental R&D in Crolles, France. He has a BSc in Physics from University College London and a Masters Degree in Telecommunications from Aston University and is a Member of the IET.

Dr. Ahsan Bootehsaz
Synopsys

Ahsan Bootehsaz is a Vice President of Engineering in the IC Implementation business group at Synopsys, Mountain View, California. He joined Synopsys in 1992 and has held various R&D management positions over the years. His R&D responsibility includes static timing and signal integrity analysis, parasitic extraction, power and reliability analysis, and formal verification equivalency checking products. Prior to joining Synopsys, he held various engineering and R&D management positions at LSI Logic Corporation, Milpitas, California.

Dr. Bootehsaz received a B.Sc. degree in Electrical and Electronic Engineering from Nottingham University, UK, and a Ph.D. in microelectronics at the University of Manchester Institute of Science and Technology, UK.

Miguel Miranda
IMEC

Miguel Miranda received the master and PhD degrees both in Telecommunications Engineering from the Technical Univ. of Madrid (Spain), respectively in 1989 and 1994. In 1995 he joined IMEC, Leuven (Belgium) where was active as senior researcher in system level design. In 2001, his R&D focus moved to Technology Aware Design (TAD) where he contributed to the fundations of this already consolidated IMEC program with current responsibilities of Senior Scientist. Miguel has (co)authored more than 80 scientific papers in peer reviewed international conferences and journals and he is author of many patents (seven of them in the area of TAD). Miguel is serving in the technical program, organizing committee and editorial board of several renowned international conferences, and journals since 2001. Currently he is project coordinator of the European-funded REALITY project and invited member of the European Design Automation Association.

Sharad Saxena
Fellow, PDF Solutions

Sharad Saxena is a Fellow at PDF Solutions. He received a B.Tech in Computer Science from the Indian Institute of Technology, Kharagpur, India and M.S. and Ph. D. in Computer Science from the University of Massachusetts at Amherst, USA. Prior to joining PDF Solutions, he was a Senior Member of Technical Staff at Texas Instruments R&D division in Dallas.

His work has been in the area of characterizing, modeling and reducing process variability in semiconductor technologies and its impact on product performance. He has been inventor or co-inventor on 15 issued patents. He has also authored or co-authored 35 papers. The papers have appeared in journals like IEEE Transactions on Electron Devices, IEEE Transactions on Semiconductor Manufacturing and IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems, and also in conferences like IEDM, VLSI Technology Symposium, CICC, and International Conference on Microelectronic Test Structures (ICMTS), International Conference on Quality in Electronic Design (ISQED). He was co-author of one of the papers that received the best paper award in ISQED-2004.

He was Associate Editor of IEEE Transactions on Computer Aided Design of Electronic Circuits and Systems from Sept 2002-Dec 2005. He has also served on the ISQED program committee. He is a Senior Member of IEEE.

Philipe Hurat
Cadence

Philippe has over 20 years of experience in the semiconductor and EDA industries in a broad range of technical and marketing roles.

Philippe is product engineer director at Cadence design systems for Cadence Litho Physical Analyzer and Litho Electrical Analizer. Before the acquisition of Clear Shape Technologies by Cadence, he was senior director of technical marketing and customer applications. Prior to Clear Shape, Philippe was responsible for marketing the Synopsys DFM and TCAD product lines, and held various technical marketing, strategic marketing, product marketing and applications engineering positions at Numerical Technologies, Cadabra Design Automation and Compass Design Automation. Philippe started his career as a design engineer at VLSI Technologies.

Philippe holds a Ph.D. in Microelectronics from INPG, National Polytechnic Institute of Grenoble, France, and an M.S. in Computer Science from the University of Joseph Fourier in Grenoble, France. Philippe has authored or co-authored numerous technical papers and patents related to design for manufacturing and physical design optimization.

Jeff Watt
Technology Architect, Altera Corporation

Jeff Watt is Technology Architect at Altera Corporation, where he oversees compact model development and new technology initiatives. Prior to joining Altera, Jeff was at Cypress Semiconductor where he served as device engineering manager and led the development of transistor processes from 0.65um to 90nm technology nodes. Jeff received his B.S. in Electrical Engineering from Queens University, Kingston, Canada in 1983 and his Ph.D. in Electrical Engineering from Stanford University in 1989. He has over 30 US patents in the areas of CMOS processing, device structures, circuits and ESD protection. He is a Senior Member of the IEEE, has served on the technical committee of the VLSI Technology Symposium and is past chairman of the Santa Clara Valley Chapter of the Electron Devices Society.

Patrick Drennan
Solido Design Automation

Patrick Drennan obtained BSEE and MSEE degrees from Rochester Institute of Technology and a PhD in Electrical Engineering from Arizona State University.

Patrick worked for 15 years at Motorola / Freescale Semiconductor in Tempe, Arizona where he was Distinguished Member of the Technical Staff. In 2007, Patrick joined Solido Design Automation as Chief Technology Officer, working on design solutions for variation.